psmmacker

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psmmacker last won the day on August 22 2016

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About psmmacker

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  • Birthday 01/04/1980

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  1. addded 2 gnds 240 volt cable and solided to 2 way hub on top also double the grounds from power pack as i helps and make grounds stronger as pictured below take note that - negative are wired together from power pack screw tap also moved voltage resister maked (201) above says v+ adj on power pack @ 4.81 volt scratched duel shield with screw driver and added gnd and solidred cable hopefully uncal sasha will add a gnd tag in rev v2.0 version thicker cable needed between power pack and panel 5volt red and black - to help noise and amp drain http://m.ebay.co.uk/itm/21-AMP-1-5mm-ROUND-12V-24V-2-Twin-Core-DC-Power-Cable-Wire-Car-LED-Light-Auto-/322538821623?var=&hash=item4b18cfd7f7%3Am%3AmdZKAKRETOvjsj2GQtjBRYQ&_trkparms=pageci%3A60e9ba41-68bc-11e7-b8e3-74dbd180c7ac%7Cparentrq%3A4235972615d0aa12eb5663e6ffe7b3f8%7Ciid%3A6 i also notice if i wire pin 16 and 8 i lost leds reverse it and they come back on p5 updated and fixed finaly pin 16 from stm to gnd of power pack also ask seller to supply 1 meter of 5 volt + cable the black -5 are tide off and split between p4 update below read this message to uncle sash to understand a fix sm5166p videos of above fix received_1336855859770118.mp4 received_1336855343103503.mp4 this also give me a idear to make a pcb dasiy chain rather then a cable one wiith 2 male hub on a pcb so pin 1 2 3 4 5 6 7 9 10 11 12 13 14 15 stay conected between stm output and panel input pin 8 and 16 wired together and add gnd from power pack to them can a special pcb be made panels that i have all tested and works Check out this recommended store on AliExpress. Find great products at low prices! http://s.aliexpress.com/63yE3yEZ Check out this recommended store on AliExpress. Find great products at low prices! http://s.aliexpress.com/NRrYZNVf wiring video and testing received_1333064116815959.mp4 received_1333062453482792.mp4 p5 remove pin 8 16 on daisy chain and between stm 32 and panel keeping pin 4 connect with gnd in the middle pin 16 and 8 on daisy chain on panel right tied off from left panel pin 4 only all pins 4 8 16 all tied off on input of panel I was also thinking of changing the gnds swaping pin 4 for 8 8 for 4 keeping 16 on the chain as 1 gnd for each red a b = gnd 4 blue a b = gnd 8 green a b = 16 incase panels are wired old video look at the top one on p5
  2. to me this means the output of the end of the panel should need some type of tappng off as it seems to be open circuit but a good gnd use for pin 4 also see the register shift as white is ok but green and red seem to be one line out of place and i know ya its useless for duel display support
  3. this is the best methood seem the pc and power pack are switching via io pin and swd pin 3 dont know why its working may need a resister or diode on i/o new update 29/06/2017 100 k resister and diod line pointing down from power pack and hook to pin pb3 where hub 75 is and pd13 on top of i/0 pins
  4. new way of sorting out interference flicking on future pinball on sash latest shield pin 1 on swd to gnd on power pack plus pin 4 swd pins was missing when it worked for vpinball mame still no gnd on the panels but stull trying to find a gnd to tie to. the shield
  5. DP5020B DP5020B Overview Package information DP5020B is designed specifically for LED display driver chip Set the CMOS shift register with the latch function that can be serial input Data is converted to parallel output data format. DP5020B operating voltage of 3.3V-5.0V, providing 16 power product name Package form Plastic body size (Mm) Foot pitch (Mm) DP5020B SSOP24 13.0 * 6.0 * 1.8 1.0 DP5020B QSOP24 8.65 * 3.9 * 1.4 0.635 DP5020B QFN24 (4 * 4) 4 * 4 * 0.85 0.5 The flow source can provide a constant power of 1mA to 32mA at each output port Flow; and a single IC chip output current difference is less than ± 2.5%; multiple IC Between the output current difference is less than ± 3.5%; channel output current does not follow the input The output voltage (VDS) changes; and the current by the voltage and the environment Pin definition The temperature change is less than 1%; the output current of each channel is of the size External resistor to adjust. DP5020B output port voltage up to 17V, so you can in every Output terminals in series with multiple LED lights; In addition, DP5020B up to 25MHz clock frequency can meet the system for a large number of data transmission needs begging. Features  16-channel constant current source output  Constant current: 1-32mA@VDD=5.0V @ Chip error <± 2.5%, inter-chip error <± 3.5% 1-22mA@VDD=3.3V @ Chip error <± 2.5%, inter-chip error <± 3.5%  The output current supports external Rext resistance adjustable  Fast output current response, OE (minimum): 35ns  Up to 25MHz clock frequency  Working voltage: 3.3V ~ 5.0V  Package form: SSOP24, QSOP24, QFN24 (4 * 4) Www.depuw.com V1.1 -1- Aug 2016 DP5020B Application areas  Advertising screen  LED lighting A simple block diagram of internal functions Pin description Function Description name GND Chip ground SDI Serial data input port CLK Clock signal input port; clock rising edge when the data is shifted Data latch control port. When LE is high, the serial data will be passed to the output latch; when LE is low, LE Material will be latched OUT0 ~ OUT15 Constant current source output port Output enable control port. When the OE is low, it will start OUT0 ~ OUT15 output; when OE is high, OE SDO R-EXT VDD OUT0 ~ OUT15 output will be turned off Serial data output port; can be connected to the next chip SDI port Connect an external resistor to the input port; this external resistor can set the output current of all output channels Chip power supply Www.depuw.com V1.1 -2- Aug 2016 DP5020B Output and input equivalent circuit  OE input  CLK, SDI input  OUT0 ~ OUT15 output LE input SDO output Www.depuw.com V1.1 3- Aug 2016 DP5020B Timing diagram Truth table Maximum limit parameter characteristic On behalf of the symbol Maximum range unit voltage VDD 0 ~ 7.0 V Input voltage VSDA, VCLK, VLE, VOE -0.4 ~ VDD + 0.4V V Current output current IOUT +45 The output voltage is applied VDS -0.5 ~ + 17.0 Clock frequency FCLK 30 IC operating ambient temperature Topr -40 ~ + 85 ℃ IC storage ambient temperature Tstg -55 ~ + 150 ℃ HBM body discharge mode VESD > 4 KV MA V MHz Note: The maximum peak temperature of the surface mount product can not exceed 260 ℃, the temperature curve according to J-STD-020 standard, refer to the actual factory and solder paste recommended by the factory to set their own. Www.depuw.com V1.1 4- Aug 2016 DP5020B DC characteristics (VDD = 5.0 V, Ta = 27 ° C) characteristic On behalf of the symbol Measurement conditions Minimum value Typical value The maximum value unit Quiescent Current IDD VDD = 5.0V, R-EXT is floating and IOUT is off - 0.9 - MA OUT port withstand voltage VDS (MAX) OUT0 ~ OUT15 - - 17 V OUT port output current IOUT VDD = 5.0V 1 - 32 MA - -twenty two - MA IOL - twenty two - MA VIH 0.7 * VDD - VDD V VIL GND - 0.3 * VDD V IOH SDO drive current VDD = 5.0V Input port rollover level OUT output current leakage current SDO output voltage OUT port output current 1 Output current error OUT port output current 2 Output current error IOH VDS = 17V - - 0.5 UA VOL IOL = + 1mA - - 0.4 V VOH IOH = -1mA 4.6 - - V MA IOUT1 DIOUT IOUT2 DIOUT VDS = 1.0V Rext = 1800Ω - 8.9 - IOUT = 8.9mA On-chip - - ± 2.5% Rext = 1800Ω Between pieces - - ± 3.5% VDS = 1.0V Rext = 920Ω - 17.5 IOUT = 17.5mA On-chip - - ± 2.5% Between pieces - - ± 3.5% VDS = 1.0V - MA VDS = 1.0V Rext = 920Ω Output current error / VDS change % / ΔVDS VDS = 1.0V to 3.0V - ± 0.5% - % / V Output current error / VDD change % / ΔVDD VDD = 4.5V to 5.5V - ± 0.5% - % / V Pull-up resistance R OE (up) OE - 200 - KΩ Pull-down resistance RLE (down) LE - 200 - KΩ IDD (off) 1 R-EXT is floating, OUT0 ~ OUT15 = OFF - 0.9 - IDD (off) 2 Rext = 1800Ω, OUT0 ~ OUT15 = OFF - 2.1 - IDD (off) 3 Rext = 920Ω, OUT0 ~ OUT15 = OFF - 3.2 - IC quiescent current Www.depuw.com V1.1 -5- MA Aug 2016 DP5020B (VDD = 3.3 V, Ta = 27 ° C) characteristic On behalf of the symbol Measurement conditions Minimum value Typical value The maximum value unit Quiescent Current IDD VDD = 3.3V, R-EXT is floating and IOUT is off - 1.2 - MA OUT port withstand voltage VDS (MAX) OUT0 ~ OUT15 - - 17 V OUT port output current IOUT VDD = 3.3V 1 - twenty two MA - -10.5 - MA IOL - 13.3 - MA VIH 0.7 * VDD - VDD V VIL GND - 0.3 * VDD V IOH SDO drive current VDD = 3.3V Input port rollover level OUT output current leakage current SDO output voltage OUT port output current 1 Output current error OUT port output current 2 Output current error IOH VDS = 17V - - 0.5 UA VOL IOL = + 1mA - - 0.3 V VOH IOH = -1mA 3.0 - - V MA IOUT1 DIOUT IOUT2 DIOUT VDS = 1.0V Rext = 1800Ω - 8.9 - IOUT = 8.9mA On-chip - - ± 2.5% Rext = 1800Ω Between pieces - - ± 3.5% VDS = 1.0V Rext = 920Ω - 17.5 IOUT = 17.5mA On-chip - - ± 2.5% Between pieces - - ± 4.5% VDS = 1.0V - MA VDS = 1.0V Rext = 920Ω Output current error / VDS change % / ΔVDS VDS = 1.0V to 3.0V - ± 0.5% - % / V Output current error / VDD change % / ΔVDD VDD = 3.3V ~ 3.8V - ± 1% - % / V Pull-up resistance R OE (up) OE - 200 - KΩ Pull-down resistance RLE (down) LE - 200 - KΩ IDD (off) 1 R-EXT is floating, OUT0 ~ OUT15 = OFF - 0.6 - IDD (off) 2 Rext = 1800Ω, OUT0 ~ OUT15 = OFF - 1.8 - IDD (off) 3 Rext = 920Ω, OUT0 ~ OUT15 = OFF - 3.0 - IC quiescent current Www.depuw.com V1.1 6- MA Aug 2016 DP5020B DC characteristic test circuit Www.depuw.com V1.1 -7- Aug 2016 DP5020B Dynamic characteristics (VDD = 5.0V) characteristic delay (Low to high) delay (High to low) Representative Measurement conditions Minimum value General value The maximum value unit CLK - OUT TpLH1 - 30 - Ns LE - OUT TpLH2 - 26 - Ns OE - OUT TpLH3 - 30 - Ns CLK - SDO TpLH VIL = GND - 28 - Ns CLK - OUT TpHL1 Rext = 1800Ω - 35 - Ns LE - OUT TpHL2 VDD = 5.0V - 33 - Ns OE - OUT TpHL3 RL = 400Ω - 35 - Ns CLK - SDO TpHL CL = 10pF - 27 - Ns VIH = VDD Current output rising edge time TOUT-RISE - 30 - Ns Current output falling edge time TOUT-FALL - 35 - Ns Minimum value General value The maximum value unit (VDD = 3.3V) characteristic delay (Low to high) delay (High to low) Representative Measurement conditions CLK - OUT TpLH1 - 42 - Ns LE - OUT TpLH2 - 36 - Ns OE - OUT TpLH3 - 45 - Ns CLK - SDO TpLH VIL = GND - 30 - Ns CLK - OUT TpHL1 Rext = 1800Ω - 38 - Ns LE-OUT TpHL2 VDD = 3.3V - 33 - Ns OE - OUT TpHL3 RL = 200Ω - 40 - Ns CLK - SDO TpHL CL = 10pF - 29 - Ns VIH = VDD Current output rising edge time TOUT-RISE - 26 - Ns Current output falling edge time TOUT-FA
  6. ya IBJ pin 4 is first gnd to point from sash also bridge all gnds across each pin on shield hence the hub 75 has weaking gnds due to thin cables being used i did have idear to add a pin4 gnd between panels panels on dasiy chian aslo vpinball usues less current on certain tables then fututre pinball hench why austin power on future pin ball and not flintstones so putting power pack gnd direct to pin 4 gnd stable it because why would u double up gnds you would need extra if the hub75 had 3 already i am i computer enginineer and good shields on pwm data paths help how do we know this flicking due to electinic static radio interfernce as every thing digital and not analoge anymore plus i think the panels should only use 2 inputs not right to left dasiy chain as i conntctiom from the hib 75 should have panel left and panel right hub 75 headers and adding 1 gnd and joining from the panels to 1 or 2 stm pins bring the pc gnd power pack and stm mcu discovery in to a stable gounding making the mcu switch with the mcu chip and usb data sync psm